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A new Front-End board for RPC detector of CMS

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1999 with 82
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C.
Binetti

R.
Liuzzi

+ 1

F.
Loddo

37.46

INFN -
Istituto Nazionale di Fisica
Nucleare

Antonio
Ranieri

53.41

INFN -
Istituto Nazionale di Fisica
Nucleare

Show more authors

Abstract

A
new Front-End board for the RPC detector of the CMS experiment at LHC is
described. It houses two Front-End chips and the Front-End controller, which
includes the Synchronization Unit. Its aim is to amplify the delta-like detector
signals, ranging from 20 fC to 20 pC, generate fast output pulses and
synchronize them with the LHC clock. Preliminary version 2 1 Introduction In the
CMS experiment for LHC physics, the Resistive Plate Chamber (RPC) detector will
give a fast trigger signal to identify muon track, measure its transverse
momentum and relate it to the correct bunch crossing. An RPC consists of two
parallel plates, made out of phenolic resin (bakelite) with a bulk resistivity
of 10 10 Wcm, separated by a gas gap of 2 millimeters. The whole structure is
made gas tight. The outer surfaces of the resistive material are coated with
conductive graphite paint to form the HV and ground electrodes. The readout is
performed by means of aluminum strips separated from the graphite
...

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Available on CMS information server CMS NOTE 1999/047

The Compact Muon Solenoid Experiment

Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland

CMS Note

March 1, 1999

A new Front-End board for RPC detector of

CMS

C. Binetti, R. Liuzzi, F. Loddo, B. Marangelli, A. Ranieri

Dipartimento Interateneo di Fisica and Sezione INFN, Bari, Italy

Abstract

A new Front-End board for the RPC detector of the CMS experiment at LHC is described. It houses two

Front-End chips and the Front-End controller, which includes the Synchronization Unit. Its aim is to amplify the

delta-like detector signals, ranging from 20 fC to 20 pC, generate fast output pulses and synchronize them with

the LHC clock.

Preliminary version

2

1 Introduction

In the CMS experiment for LHC physics, the Resistive Plate Chamber (RPC) detector will give a fast

trigger signal to identify muon track, measure its transverse momentum and relate it to the correct bunch

crossing. An RPC consists of two parallel plates, made out of phenolic resin (bakelite) with a bulk resistivity of

10

10

Ωcm, separated by a gas gap of 2 millimeters. The whole structure is made gas tight. The outer surfaces of

the resistive material are coated with conductive graphite paint to form the HV and ground electrodes. The read-

out is performed by means of aluminum strips separated from the graphite coating by an insulating PET film.

The RPC proposed for CMS is made of two gaps with common pick-up strips in the middle, the so called

double gap RPC, in this case the total induced signal read out by the Front End electronics is the sum of the two

single-gap signals.

The RPC will be operated in the so-called avalanche mode or low gain mode of operation for sustaining

an event rate as high as 1000 Hz/cm

2

[1].

In the low gain mode of RPC operation, a fraction of the detector amplification is transferred to the Front-

End electronics, reducing the charge produced by a single ionizing particle to few tens of fC and increasing, at

the same time, the detector rate capability.

The Front-End chip must be capable to preserve the excellent RPC timing response characteristics

(typically 1-2 ns) [2]. Moreover, this new F.E. board deals with another crucial issue for the triggering purposes,

that is the synchronization of the F.E. signals.

2 The Front-End Chip

The F.E. chip, named FEC in the following, is designed in the Maxim SHPI bipolar process and its aim is

to amplify the RPC signals and generate fast output pulses for timing. The chip prototypes were mounted on a

preliminary version of the FE board and tested in the September 1997 at CMS-H2 beam line at CERN-SPS. The

performance of the entire system (RPC plus FEC), in terms of pulse resolution, timing performances, cluster size

and noise characteristics were encouraging [3].

The chip consists of six channels of two-stage amplifier, threshold discriminator, one-shot and line-driver,

as shown in Fig.1.

In

V

test Preamplifier

Gain stage

Out

p

Out

m

V

th

V

drive

Discriminator

One-Shot

Driver

Fig.1. Block diagram of one FEC channel

The transimpedance preamplifier has 30 Ω input impedance for strip impedance matching and a dominant

pole at 180 MHz. It is capable to preserve the excellent timing information of the input signal, which is similar to

a delta-like current signal ranging from 20 fC to 20 pC. A differential amplifier, having an 18 MHz dominant

pole and providing 30 ns output pulse tail follows the input stage. The overall charge sensitivity is 1.6 mV/fC,

while the Equivalent Noise Charge is less than 2 fC.

The amplifier is then DC coupled to a leading-edge discriminator, with a threshold regulation ranging

from 10 fC to 300 fC. A monostable with adjustable pulse width has also been introduced to avoid triggering on

after pulses which can occur in the RPC. The width can be set from 50 ns to 200 ns and in our case its typical

value is 100 ns.

Finally a differential line driver is included which drives an LVDS signal over twisted pair copper. The

signal has a voltage level of 250 mV on 110 Ohms.

The total power consumption is about 30 mW/channel and the crosstalk measured on the test bench

(without the connection RPC-FEC) resulted to be less than 1%. A typical transient response of the F.E. chip is

shown in Fig. 2.

3

0

-20

-40

-60

40

0

-40

1.3

1.2

1.1

1.0

Amplifier output

mV

V

ns

0 20 40 60 80

uA

Input current signal (50 fC)

Driver output

Fig.2. Typical transient response of the FEC

2. The F.E. board

The front-end board houses 2 FECs and a Front-End Control Circuit (FECC). The FECC, whose block

diagram is shown in Fig. 3, must provide the threshold voltages and test pulses to the FECs and synchronizes the

Front-End signals with the system clock.

DAC

VTH

Serial In

Test CK

Serial to Parallel SR

Slow CK

LATCH

F

I

F

O

S

R

Lwrite

FIFO R/W

Serial Out

SU

CK(40 MHz)

IN

WINDOW

12

12

OUT

4

Test

4

Fig.3. F.E. Control Circuit block diagram

The threshold voltages are provided by two dual 10-bit DACs, with voltage output, 3-wire Serial

Interface and Low Power Consumption (3 mW). The value of the output voltage is

word

V

V

ref

TH

*

1024

2

=

where V

ref

= 500 mV is the voltage reference and word is the input digital word to the DAC. The relationship

between V

TH

and the charge threshold is [2]:

QfC

VmV

TH

TH

[]

[]

.

=

32

~ 0.3 fC/bit.

The test FIFO is a 512x18-memory device, which can be preloaded with patterns of test bits and used to

send test pulses to the FECs with a 40 MHz read clock. Inside the FEC, three channels share the same test input

so only 4 bits of the FIFO words are used. This large FIFO was chosen just for its timing performances, to cope

with the 40 MHz speed requirements. The LVTTL outputs of the FIFO are differentiated by 200 fF capacitors

inside the FEC and generate a charge pulse ~ 600 fC.

4

2.1 The Synchronization Unit

Good time performance is crucial for triggering with high efficiency at the LHC conditions. The

propagation time of the signals coming from the RPC at the output of the FE has 4 contributions:

T

tot

= T

flight

+ T

RPC

+ T

prop

+ T

FE

.

T

flight

is due to the time of flight of the particle from the interaction point to detector. T

RPC

depends on the

processes of signal generation inside the RPC and on the drift towards the electrodes and T

prop

represents the

signal propagation time along the read-out strip towards the FECs.

Finally T

FE

represents the delay time introduced by the amplification and discrimination process which is

affected by three main sources of uncertainties. The first one related to the “time-walk” due to the leading-edge

discrimination method used. The second one due to the limited gain-bandwidth product of the discriminator

which introduces the dominant contribution of error at small charge overdrive. The last one is the “time-jitter”

due to the electronic noise which in our case, in terms of equivalent noise charge (ENC), is less than 2 fC.

The total σ = 0.7 ns of T

FE

, can be obtained by weighting the signal time distribution with the probability

of occurrence of each charge value given by the charge spectrum (Fig.4) [2].

Fig. 4 Experimental T

FE

time distribution

Experimental results show that the total time distribution (T

TOT

) of the RPC signals, considering all the

effect for the CMS detector described before, exhibits a gaussian behavior with a σ = 1.7 ns and with a base

which does not exceed 20 ns, well within the LHC bunch crossing separation time (25 ns) [3][4].

In order to prevent further time degradations and achieve correct bunch crossing assignments, it is

necessary to synchronize the signals with the 40 MHz LHC clock near the detector and before their transmission.

In this way, the trigger processor can deal with signal related to the same bunch crossing [5][6].

The Synchronization Unit was implemented into a FPGA device and accepts 12 output signals coming

from the two FECs after their conversion to TTL levels. The principle of operations of SU is shown in Fig. 5

.

5

CK

WIN

IN

OUT

TW

1

1

2

25 ns

Tpos

25 ns

12

Fig.5 Principle of operations of the SU

From the LHC clock, named CK, a Window named WIN is derived. When the rising edge of the input

pulse is in coincidence with a high level of WIN, then it is accepted and synchronized with the leading edge of

CK after two clock periods, otherwise it is suppressed. The WIN must be centred at the average arrival time of

the signals, while its width T

W

must be set as trade-off between the need to contain the time jitter of the signals

and that to cut as much as possible the noise. T

W

and T

pos

can be adjusted from 0 to 25 ns with 1 ns step.

In Fig. 6 the schematic diagram of one channel of the implemented synchronizer is shown, while Fig. 7

represents the typical output on the display of the oscilloscope. The signals shown are in NIM logic so a high

level on the display represents a low signal level and viceversa.

The TTL outputs of the synchronizer are then converted into LVDS levels for their transmission on

twisted pair cable. For test purposes, also the outputs of the FECs, before the synchronization, are available on an

output connector.

IN

WIN

CK

OUT

D Q

CE

CK

D Q

CK

D Q

CK

D Q

CK

Fig.6. One channel of the synchronizer

Fig.7. Test results of Synchronizer

6

Conclusions

The Front-End Board was successfully used at CERN on the test beam in the summer 1998 at the GIF

(Gamma Irradiation Facility) area. Next developments of the Front End Electronics for RPCs are under

evaluation. A new Front-End chip has been developed and the first test results on prototypes are expected in the

early summer of 1999. This new chip will have 8 channels, so the next implementation of FE board will house

16 channels. It is under evaluation also the possibility of inserting the test FIFO inside the same FPGA housing

the SU. In such a way, the next implementation of the circuit is expected to be cheaper and more compact.

We would like to thank the Bari RPC-CMS Group, which gave us the possibility to carry out the project

and, for their useful contributions in the electronic setup, Mr. Michele Papagni and Mr. Carlo Pinto.

References

[1] CMS Collaboration, “CMS Muon Technical Design Report” CERN/LHCC 97-32, 15 December 1997.

[2] F. Loddo et. al., “Front End electronics for RPC detector of CMS”. Proceedings of the IV International

Workshop on Resistive Plate Chambers and related detectors, Napoli, October 15-16, 1997.

[3] M. Abbrescia et. al., “Beam test results on double-gap resistive plate chambers proposed for CMS

experiment”. Nucl. Instr. And Meth. A 414 (1998) 135-148.

[4] M. Abbrescia et. al., “Local and global performance of avalanche operated double gap Resistive Plate

Chambers for the CMS experiment”. Submitted to Nucl. Instr. And Meth.

[5] G. Bruno, “A simulation study of the RPC muon trigger for CMS”. Proceedings of the IV International

Workshop on Resistive Plate Chambers and related detectors, Napoli, October

15-16, 1997; CMS Internal

Note 1998/0004.

[6] G. Wrochna, “Synchronization of the CMS Muon Detector”. CMS Conference Report 1998/017. Talk given

at IV Workshop on Electronics for LHC Experiments, Rome, 21-25.09.1998.

Citations (2)Citations (2)

References (5)References (5)

...
The contribution from the front-end electronics is negligible, but the
time of RPC response has a quasigaussian distribution with σ RPC <
3.0-3.5ns as measured in recent RPC prototypes tests [11].
These data indicates that the correct bunch crossing can be assigned with 99%
efficiency. ...

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